This invention relates generally to silicon controlled rectifiers (SCRs) as used for electrostatic discharge (ESD) protection in integrated circuits, and in particular, to an SCR structure having a breakdown voltage that is triggered by a vertical zener structure to provide much lower threshold voltage.
The protection of integrated circuits against electrostatic discharge (ESD) is an important design consideration for integrated circuits. Integrated circuits are often susceptible to electrostatic discharge. For instance, substantial electrostatic charges can accumulate on a person""s body during regular daily activities, such as walking on a carpet. If such a person subsequently comes in contact with a grounded integrated circuit, the charges on the person can discharge through that integrated circuit. Such a discharge produces a relatively large current which can cause damage to the integrated circuit.
In order to reduce the likelihood of damage to integrated circuits due to electrostatic discharge, ESD protection circuits or devices are designed into integrated circuits. One such device is a silicon controlled rectifier (SCR). An SCR is a semiconductor device consisting of an anode terminal followed by p-n-p-n doped layers and then a cathode terminal. The second p-doped layer typically serves as a control terminal for receiving a voltage which governs the current (or conduction) from the anode to the cathode.
As an ESD device, the control terminal typically is tied to the cathode of the SCR, and the SCR is typically connected across the integrated circuit input/output pad and ground potential. During an ESD event, sufficient amount of charges build-up on the integrated circuit input/output pad that causes the SCR to rapidly breakdown and conduct current with a very low intrinsic resistance. The rapid conduction of the SCR causes the charges on the integrated circuit input/output pad to discharge through the grounded cathode of the SCR. This action prevents the excessive charge from damaging the integrated circuit.
FIG. 1 illustrates a side cross-sectional view of a prior art SCR 100. The SCR 100 comprises a p-doped substrate 102 and an n-doped well 104 formed within the substrate 102. The SCR 100 further includes spaced-apart p+ doped region 106 and n+ doped region 108 formed within the n-well 104. Additionally, the SCR 100 further includes spaced apart p+ doped region 110 and n+ doped region 112 formed within the p-substrate 102. A field oxide layer 114 separates the p+ doped region 110 from the n+ doped region 112, and another field oxide layer 116 separates the n+ doped region 112 from the n-well 104.
To serve as an ESD protection device, the p+ region 106 and n+ region 108 of the SCR 100 are typically connected to the input/output pad, and the p+ region 110 and n+ region 112 are typically connected to Vss. When an ESD event occurs, the SCR 100 breakdowns at the junction of the p-substrate 102 and the n-well 104.
A problem with the prior art SCR 100 is that its breakdown voltage is too high to provide adequate protection of the integrated circuit. It is a trend in the semiconductor field to reduce the size of device structures, also reducing gate oxide thickness. Although the size reduction of device structures makes better efficient use of integrated circuit area, the structures are more susceptible to ESD damage due to their smaller geometry and thinner gate oxide. Thus, in order to better protect these structures, an SCR with a lower breakdown voltage would be more desirable. Consequently, recent prior art SCRs have been developed that provides lower breakdown voltages.
FIG. 2 illustrates a side cross-sectional view of a prior art SCR 200 that includes a mechanism for triggering breakdown at a lower voltage. The SCR 200 has been termed in the relevant art as a medium voltage triggered SCR (MVTSCR). Similar to SCR 100 discussed above, SCR 200 comprises a p-substrate 202 having an n-well 204, spaced apart p+ region 206 and n+ region 208 formed within the n-well 204, spaced apart p+ region 210 and n+ region 212 formed in the p-substrate 202, and a field oxide 214 separating the p+ region 210 from the n+ region 212.
To provide a lower breakdown voltage, the SCR 200 further includes an n+ region 218 which bridges the n-well 204 with the p-substrate 202. A field oxide 216 is provided between n+ regions 212 and 218. This SCR has an advantage of providing a lower breakdown voltage due to the added n+ region 218. However, the breakdown voltage is still not low enough to provide adequate protection. Also, the SCR 200 has a disadvantage of having the breakdown occur along a small region near the interface of the n+ region 218 and the field oxide 216, which limits its current handling capability.
FIG. 3 illustrates a side cross-sectional view of another prior art SCR 300 that also includes a mechanism for triggering breakdown at a lower voltage. The SCR 300 has been termed in the relevant art as a low voltage triggered SCR (LVTSCR). Similar to SCRs 100 and 200 discussed above, SCR 300 comprises a p-substrate 302 having an n-well 304, spaced apart p+ region 306 and n+ region 308 formed within the n-well 304, spaced apart p+ region 310 and n+ region 312 formed in the p-substrate 302, a field oxide 314 separating the p+ region 310 from the n+ region 312, and an n+ region 318 bridging the n-well 304 with the p-substrate 302.
To provide an even lower breakdown voltage, the SCR 300 further includes a gate polysilicon 320 to trigger breakdown. Similarly, this SCR has an advantage of providing a lower breakdown voltage due to the added gate polysilicon 320. However, the breakdown voltage is still not low enough to provide adequate protection. Also, the SCR 300 has a disadvantage of having the breakdown occur along a small region near the interface of the n+ region 318 and the gate polysilicon 320, which limits its current handling capability. Also, structure 300 makes the integrated circuit more difficult to design and to manufacture due to the newly added MOSFET device 320.
FIG. 4 illustrates a side cross-sectional view of yet another prior art SCR 400 that also includes a mechanism for triggering breakdown at a lower voltage. Similar to the previous SCRs, SCR 400 comprises a p-substrate 402 having an n-well 404, spaced apart p+ region 406 and n+ region 408 formed within the n-well 404, spaced apart p+ region 410 and n+ region 412 formed in the p-substrate 402, and a field oxide 414 separating the p+ region 410 from the n+ region 412.
To provide an even lower breakdown voltage, the SCR 400 further includes a lateral zener junction 417 comprised of p+ region 418 adjacent a deeper n+ region 420. The lateral zener junction is separated from the n+ region 412 by field oxide 416, and separated from the n-well 404 by field oxide 422. Similarly, this SCR has an advantage of providing a lower breakdown voltage due to the added zener junction 417 which triggers the breakdown of the SCR 400. However, the SCR 400 still has the disadvantage of having the breakdown occur along a thin plane region at the interface of the p+ region 418 and the deeper n+ region 420, which limits its current handling capability. Also, the process related to this structure could be more complex.
Thus, there is a need for an SCR that can be triggered at a relatively low voltage to provide better ESD protection of integrated circuit structures, including thin gate oxides. Also, there is a need for an SCR whose breakdown voltage can be easily set by a simple process procedure. In addition, there is a need for an SCR that has a higher current handling capability.
The above-identified needs are satisfied with a new and improved silicon controlled rectifier (SCR) in accordance with the invention. The SCR of the invention comprises a vertical zener junction which serves as a mechanism for triggering breakdown. The vertical zener junction can be easily designed to provide a relatively low breakdown voltage for the required protection, which typically lies above the maximum Vdd and below the gate oxide breakdown voltage. The vertical zener junction, which includes a p+ doped region sandwiched between two n+ doped regions, can be easily designed to trigger the breakdown at a desired voltage by adjusting the doping concentration of the region (either the p+ or n+ doped region) having the lesser doping concentration. Also, the SCR of the invention has improved current handling capability since the breakdown occurs throughout the p+ region, which makes the SCR more reliable and robust.
More specifically, the SCR of the invention comprises a p-doped substrate having an n-doped well, spaced apart p+ and n+ doped region formed within the n-doped well, and spaced p+ and n+ doped regions formed within the p-substrate external to the n-doped well. The SCR further includes a vertical zener junction to assist the triggering of the breakdown in the SCR. The vertical zener junction comprises a p+ doped region sandwiched between two n+ doped regions. The vertical zener junction is situated between the n-doped well and the n+ doped region of the SCR anode.
The n+ doped region of the vertical zener diode closest to the n-doped well, could be at least partially formed within the n-doped well or can be form outside of the n-doped well. In the exemplary implementation, the p+ doped region of the vertical zener junction extends deeper into the p-substrate than its two n+ doped regions. The SCR may further include respective field oxides between the anode p+ and n+ doped regions, between the anode n+ doped region and the vertical zener junction, and between the vertical zener junction and the n-doped well.